Typical integrated memory devices include arrays of memory cells arranged in rows and columns. In many such memory devices, several redundant rows and columns are provided to replace malfunctioning memory cells found during testing. Testing is typically performed by having predetermined data values written to selected row and column addresses that correspond to memory cells. The memory cells are then read to determine if the data read matches the data written to those memory cells. If the read data does not match the written data, then those memory cells are likely to contain defects which will prevent proper operation of the memory device.
The defective memory cells may be replaced by enabling the redundant circuitry. A malfunctioning memory cell in a column or a row is substituted with a column or row of redundant memory cells. Therefore, a memory device need not be discarded even though it contains defective memory cells. Substitution of one of the redundant rows or columns is accomplished in a memory device by programming a specific combination of fuses, or if the memory device uses antifuses, by programming a specific combination of antifuses, located in one of several fuse or antifuse blocks in the memory device. Conventional fuses are resistive devices which may be opened or broken with a laser beam or an electric current. Antifuses are capacitive devices that may be closed or blown by breaking down a dielectric layer in the antifuse with a relatively high voltage.
A specific combination of antifuses are programmed to correspond to an address of a row or column having defective memory cells. For example, if the defective row or column has a 11-bit binary address of 10010010010, then the antifuses in a set of 11 antifuses are programmed to store this address. The sets of antifuses are typically arranged in an antifuse block with the number of antifuses equal to the product of the number of address bits per a row or column address and the number of redundant rows or columns available for memory repair. The memory device contains several antifuse blocks, each block typically corresponding to a redundancy “plane,” that defines the available redundant memory associated with a particular portion of a memory array. For example, the memory array of modern memory devices are often divided into individually addressable banks of memory, with each bank of memory typically further segmented into smaller regions, or blocks of memory. Each memory block includes a limited amount of redundant rows and columns of memory that can be used to repair defective memory in the memory block. An antifuse block is used to program the rows and columns of memory for the memory block that are mapped to redundant rows and columns of memory, respectively.
Each row or column address received by a memory device is compared to the programmed addresses that have been mapped to redundant row or column memory, respectively. Comparison of received memory addresses to the programmed addresses of the antifuse blocks is transparent to the user and is made by redundancy decoder circuitry coupled to the antifuse blocks. The redundancy decoder circuitry includes redundancy comparison logic for each antifuse block in a bank of memory. As previously discussed, a bank of memory is typically subdivided into blocks of memory, each of which has an antifuse block for programming the row and column addresses of memory within the memory block that will be mapped to redundant rows and columns of memory in the associated redundancy plane. When row and column addresses for an activated bank of memory are received, they are compared by the redundancy comparison logic for each of the antifuse blocks. If an address match is detected by one of the redundancy comparison logic, a match signal MATCH is generated to indicate that memory has been remapped to redundant memory for that memory block and the MATCH signal is provided to an address decoder, either row or column, to activate the appropriate row or column of redundant memory. After comparison, the row of memory corresponding to the row address, or the redundant row of memory to which the row address is mapped, is activated for one of the memory blocks, and the column of memory corresponding to the column address, or the redundant column of memory to which the column address is mapped is activated for the same memory block. A memory operation is then performed on the accessed memory location at the intersection of the selected row and column of memory.
As the memory address changes, and each new address is compared against the addresses programmed in each antifuse block, switching currents result from each new address applied to the redundancy comparison logic. Although only one block of memory will have the memory location corresponding to the row and column address, the memory addresses are nevertheless compared to the addresses programmed in each antifuse block of an activated bank of memory. For example, after decoding a row address and activating the row of memory in one of the memory blocks of a bank of memory, the column address will be compared to the addresses programmed in all of the antifuse blocks of the bank of memory, although the activated row of memory is associated with only one of the memory blocks. The switching currents resulting from the comparison of the column address by the redundancy comparison circuits for the antifuse blocks of all the other memory blocks of the bank of memory results in unnecessary power consumption. The problem with switching currents is exacerbated by “burst modes” of synchronous memory devices where a row of memory remains activated while new column addresses are provided every clock cycle in order to quickly read data from or write data to the activated row of memory. With each new column address, the switching currents from the unnecessary comparison of the column addresses by the redundancy comparison circuits for the memory blocks not having the activated row of memory are wasted.
Therefore, where minimizing unnecessary power consumption is desirable, alternative methods and systems for performing address comparison to addresses programmed by fuses, or antifuses, such as in memory applications for programming redundant memory, would be preferable.